1. Field of the Invention
The present invention relates to a semiconductor manufacturing process and in particular to a method of forming a dynamic random access memory (DRAM) comprising deep trench capacitors and partial vertical transistors.
2. Description of the Related Art
When manufacturing memory products such as trench-type DRAM, stacked-type DRAM and FLASH memory, in order to reduce the size of a chip, the conventional semiconductor process uses self-aligned contact (SAC) technology to define a reduced distance between two adjacent gate conductive structures.
A DRAM structure comprising a trench capacitor and a vertical transistor is shown in FIG. 1. A deep trench 18 is formed in a substrate 10 comprising silicon. A trench capacitor 14 is formed in the lower portion of the deep trench 18.
A diffusion region is formed in the substrate 10 between the trench capacitor 14 and the vertical transistor 16 as a buried strap 12. The buried strap 12 is formed by driving the dopant in an electric layer (not shown) into the substrate 100 during a thermal process.
The trench top oxide (TTO) 24 is deposited on the upper electrode to electrically isolate the trench capacitor 14 and the vertical transistor 16.
The vertical transistor 16 comprises a source 26, a drain 12, a gate oxide layer 28, and a gate layer 20. The gate layer 22 extends from the surface of the deep trench 18 to the substrate 100.
However, the corner 30 of the gate oxide layer 28 is usually thinner than the vertical sidewall of the deep trench 18 and the surface of the substrate 100 because of the different rate of oxidation. Thus, performance of the vertical transistor 16 is affected.